1. Field of the Invention
The present invention relates to semiconductor memory devices and operating methods thereof, and more particularly, to a semiconductor memory device capable of operating at a high speed and an operating method thereof.
2. Description of the Background Art
A general dynamic random access memory (referred to as DRAM hereinafter) includes a memory cell array comprising a plurality of memory cells arranged in rows and columns. In writing or reading data., one row of the memory cell array is selected in response to a row address signal which is applied externally, and one column of the memory cell array is selected in response to a column address signal which is applied externally. Data is written in a memory cell located at the intersection of the selected row and column, or read out of the same.
In a DRAM which receives a duplexed address signal of a row address signal and a column address signal, an externally applied row address strobe signal RAS is activated so that the row address signal is accepted, and an externally applied column address strobe signal CAS is activated so that the column address signal is accepted.
In addition, a nibble mode is used to obtain a higher operating speed of the DRAM. In the nibble mode, writing or reading of data is performed in such a manner that after the row address strobe signal RAS and the column address strobe signal CAS are once activated (or put in the low level), only the column strobe signal CAS is put in an active state (low level) and in an inactive state (high level) by turns repeatedly. In other words, since in the nibble mode the writing or reading operation of data is performed regarding the time when the column address strobe signal CAS is put in the active state as a starting point, it is possible to attain a higher operating speed than a general reading operation regarding the time when the row address strobe signal RAS is put in the active state as a starting point.
A nibble mode of a conventional DRAM will be described with reference to timing charts in FIGS. 10 and 11. The nibble modes are disclosed, for example, in the Japanese Patent Publication No. 18837/1986 and the U.S. Pat. No. 4,344,156.
In FIGS. 10 and 11, the row address strobe signal RAS transits from the high level to the low level so that the operation of the DRAM is activated, and at the same time, the DRAM accepts only a row address signal out of a duplexed address signal. As a result, the corresponding row address (X.sub.n) of the memory cell array is selected. When the duplexed address signal changes to a column address signal, the corresponding column address (Y.sub.n) of the memory array is selected in response to the column address signal.
Assuming that writing operation is designated by a reading/writing designating signal at this moment, a memory cell located at the intersection (X.sub.n, Y.sub.n) of the row and column addresses selected as described above is selected, and at the same time, the memory cells of addresses (X.sub.n, Y.sub.n+1), (X.sub.n, Y.sub.n+2) and (X.sub.n, Y.sub.n+3) on the same row are selected.
As shown in FIG. 10, when the column address strobe signal CAS transits in turn from the high level to the low level, an input data D.sub.IN is written in one of the four memory cells which corresponds to the address (X.sub.n, Y.sub.n).
Additionally, while the row address strobe signal RAS is held in an active state (low level), the column address strobe signal CAS is once put in the inactive state (high level) and again in an active state so that the input data D.sub.IN is written in a memory cell corresponding to the address (X.sub.n, Y.sub.n+1) Similarly, while the row address signal RAS is held in the active state, the operation of putting the column address strobe signal CAS in the inactive state and the active state alternately is repeated, so that the data are sequentially written in the memory cells corresponding to the addresses (X.sub.n, Y.sub.n+2) and (X.sub.n, Y.sub.n+3).
Thus, the input data is written in during a cycle time t.sub.NC of the column address strobe CAS with respect to the second and further subsequent fallings of the column address strobe signals CAS so that a higher writing speed is obtained than in a case where the writing is performed during a cycle time t.sub.WC of the row address strobe signal RAS. In the products which have been currently offered for practical use, the ratio between the time t.sub.WC and the time t.sub.NC is about 4 to 1 so that the writing speed of the second through fourth data is four times as fast as that of the first one.
Meanwhile, assuming that reading operation is designated by the reading/writing designating signal, data in the memory cell at the intersection (X.sub.n, Y.sub.n) of the row address and column address selected as described above is accepted by one of four output latch circuits (not shown). At the same time, the data in the memory cells at the addresses (X.sub.n, Y.sub.n+1), (X.sub.n, Y.sub.n+2) and (X.sub.n, Y.sub.n+3) on the same row are accepted by the remaining respective three output latch circuits.
When the column address strobe signal CAS transits in turn from the high level to the low level, one of the four data accepted by the four output latch circuits which corresponds to the address (X.sub.n, Y.sub.n) is read out at an output terminal as an output data D.sub.OUT. This data is read out when the time of t.sub.RAC has passed from the transition of the row address strobe signal RAS and also when the time of t.sub.CAC has passed from the transition of the column address strobe signal CAS.
Additionally, while the row address strobe signal RAS is held in the active state (low level), the column address strobe signal CAS is once put in an inactive state (high level) and again in an active state so that one of the data accepted by the output latch circuits which corresponds to the address (X.sub.n, Y.sub.n+1) is read out at an output terminal as the output data D.sub.OUT. Similarly, while the row address signal RAS is held in the active state, the operation of putting the column address strobe signal CAS in the inactive state and the active state alternately is repeated so that the data corresponding to the addresses (X.sub.n, Y.sub.n+2) and (X.sub.n, Y.sub.n+3) are sequentially read out as the output data D.sub.OUT.
Thus, the output data are read out from the output latch circuits with respect to the second and further subsequent fallings of the column address strobe signal CAS, which results in the reduced reading time of t.sub.CAC. In the products which have been currently offered for practical use, the ratio between the time t.sub.RAC and the time t.sub.CAC is about 4 to 1 so that the reading speed of the second through fourth data is four times as fast as that of the first one.
As described in the foregoing, in the conventional nibble mode of DRAM, only three bit data of the four bit data are written in or read out at a higher speed. In order to increase the number of data written in at a higher speed, it might be effective to increase the number of memory cells to be selected first simultaneously and also the number of data input/output line pairs connected thereto. Also, in order to increase the number of data read out at a higher speed, the number of the output latch circuits might be increased advantageously. However, the output latch circuits and the data input/output line pairs have a relatively large occupied area so that there arises a problem of increased size of the integrated circuit chip and thus the increased cost thereof.